1. Field of the Invention
This invention relates to sample and hold circuits in general and, more particularly, to high-speed MOS sample and hold circuits.
2. Description of the Prior Art
Sample and hold (S&H) circuits are widely used in signal processing applications. There are many different designs, but all generally rely on an input switch to couple the input signal to be sampled to a storage device, which usually includes a capacitor. When the input signal is to be "held", the switch opens and a voltage approximately equal to the last value of the input signal is stored on the capacitor.
The degree of accuracy of the held signal value relative to the actual input signal value is largely a function of the resistance of the input switch and the time allocated for the sample. For the sample to be accurate with slowly varying signals, the time allocated for the sample must be many times the time constant of the sample and hold circuit, R.times.C, where R is the effective resistance of the input switch (which includes the resistance associated with the input signal driver to the input switch) and C is the effective capacitance of the storage capacitor (which includes any stray capacitance, Miller capacitance, etc.) and is usually a fixed value. The longer the sample time or the shorter the R.times.C time constant, the more the accuracy of the sample. For accurate acquisition of a sample, the sample time must be much greater than the time constant. A typical minimum sampling time of the five or more time constants are needed for better than a 0.1% sampling accuracy. Alternately, the time constant can be made smaller by making the capacitor smaller, but clock feedthrough and charge injection from the switches would increase.
The typical approach to increasing the speed and/or accuracy of a S&H circuit is to reduce the resistance of the input switch. Increasing the size of the MOS transistors in the switch have reduced the resistance but at the cost of increasing clock feedthrough and charge injection, both of which decrease the accuracy of the S&H.
In real-world applications, the input signal is time-varying and the sampling must be done at a high rate, such as near the Nyquist rate. Thus, the amount of time that can be allocated for the sample is short with a corresponding degradation in accuracy. In some applications, such as very high speed analog-to-digital converters or analog sampled data systems, the conventional S&H with the above improvements may not be accurate enough at the desired sampling rate.
Thus, it is desirable to provide a S&H circuit that allows for higher sampling rates than previous S&H circuits.
Further, it is desirable to provide a S&H circuit with higher accuracy at a given sampling rate than previous S&H circuits.